Semiconductor storage device

ABSTRACT

A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit  2  controls n-channel transistors  3 C,  4 B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors  3 C,  4 B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit  3  and a boost circuit  4 ) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit  3  and the boost circuit  4.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device whichneeds a refresh operation for stored data, and more particularly to atechnique for reducing a consumption of current by a system of circuitsassociated with refresh operation.

BACKGROUND ART

A pseudo-SRAM has conventionally been utilized for a portable device,wherein the pseudo-SRAM has both an advantage of a DRAM (Dynamic RandomAccess Memory) suitable for a large capacity and another advantage of anSRAM (Static Random Access Memory) making it easy to design timings. Inthe field of this type, requests for scaling down the device and forimproving long life-time of a battery have been on the increase year byyear. The pseudo-SRAM comprises a basic structure of DRAM, wherein apower consumption thereof is not necessarily small as compared to thegeneral-purpose SRAM, for which reason it had been desired to realize afurther reduction in the power consumption of the pseudo-SRAM.

An example of the conventional technique for reducing the currentconsumption will, hereinafter, be described.

FIG. 1 shows an example of a circuit for reducing the consumption ofcurrent in accordance with the prior art. In this example, the circuitis configured in order to suppress the consumption of current by anoperating circuit 501 in a stand-by state, wherein an n-channel MOStransistor (hereinafter referred to as n-channel transistor) 502 to becontrolled into an OFF-state in a stand-by state is inserted intobetween the operating circuit 501 and a ground, while a power VDD isdirectly supplied to the operating circuit 501, wherein a voltagereduction is made thereto for suppressing an operating current.

A chip select signal CS is supplied to a gate of an n-channel transistor502. The chip select signal CS is a control signal for switch betweenthe stand-by mode and an active mode. A low level of this signal placesthe semiconductor memory device integrating the operating circuit 501into the stand-by state.

The operating circuit 501 comprises basic gate circuits such asinverters and NAND-gates comprising CMOS (Complimentary Metal OxideSemiconductor). Gate threshold voltages of an n-channel transistor and ap-channel MOS transistor (hereinafter referred to as p-channeltransistor) are set relatively low in response to the reduced voltagelevel of the power VDD. In contrast, a gate threshold voltage of then-channel transistor 502 is set relatively high in consideration of asub-threshold current which provides a leakage of current.

In accordance with this configuration, in the active state, the chipselect signal CS is in the high level to place the n-channel transistor502 in the ON-state, whereby the ground voltage is supplied through thistransistor 502 to the operating circuit 501, and thus the operatingcircuit 501 is in the operable state. Since the gate threshold voltagesof the n-channel and p-channel transistors of the operating circuit 501are set low, the operating circuit 501 shows a high speed switchingoperation even by the reduced voltage of the power VDD.

In contrast, in the stand-by state, the chip select signal CS is in thelow level, thereby placing the n-channel transistor 502 into theOFF-state. Since the gate threshold voltage of the n-channel transistor502 is set high, the sub-threshold current of this n-channel transistor502 is effectively suppressed, thereby suppressing effectively a leakageof current flowing through the operating circuit 501 in the stand-bystate. Since the gate threshold voltage of the n-channel transistor 502is set high, the n-channel transistor 502 shows a delayed switchingoperation. In the active state, the n-channel transistor 502 is placedin the ON-state, so that the n-channel transistor 502 does not disturbthe switching operation by the operating circuit 501.

The voltage reduction to the power VDD for the operating circuit 501 andthe low gate threshold voltage of the transistors of the operatingcircuit 501 render compatible both the reduction to the operatingcurrent and the high speed operation in the active mode. Supplying theground voltage through the n-channel transistor 502 having the high gatethreshold voltage to the operating circuit 501 reduces the leakage ofcurrent of the operating circuit 501 in the stand-by mode.

Meanwhile, the above-described pseudo-SRAM has memory cells configuredsimilarly to the DRAM, for which reason independently from the operatingmodes, cyclic refresh operations for data stored in memory cells arenecessary. In the pseudo-SRAM, a system of circuits associated with therefresh operation remains always activated independently from theoperating modes. This causes increasing the consumption of power of thepseudo-SRAM. Particularly, there is a problem with a remarkable leakageof current as an unnecessary consumption of current in an interval oftime period (between refresh operations) which is much longer than atime necessary for cyclic executions of refresh operations.

The above-described prior art is applicable to a system of circuitsinactivated in the stand-by mode but not applicable to another system ofcircuits which may be activated in the stand-by mode such as the systemof circuits associated with the refresh in the pseudo-SRAM, wherein anyeffective reduction to the stand-by state can not be obtained.

The present invention was made in view of the above-describedcircumstances. Accordingly, it is desirable to provide a semiconductormemory device capable of effectively reducing the consumption of currentof the system of circuits associated with the refresh operation.

SUMMARY OF THE INVENTION

In order to solve the above-described issues, the present invention hasthe following constitution.

In accordance with the present invention, a semiconductor memory deviceconfigured to automatically refresh data stored in memory cells withtimings matched over plural operation modes and to allow an externalasynchronous access, wherein a leak breaking means is provided forbreaking a leak path between a system of circuits associated withrefresh operations and either a power source or a ground in an intervalof time period of the refresh operations.

In accordance with this configuration, in the interval of time periodbetween the refresh operations to be executed independently from theoperating modes, the leak path of the system of circuits associated withthe refresh operations is broken down, so that a consumption of currentof this system of circuits is limited to a consumption of currentgenerated in periods of time of actual fresh operations. The time of therefresh operation is sufficiently shorter than the interval of timeperiod between the refresh operations and a refresh cycle time, forwhich reason the consumption of current of the system of circuitsassociated with the refresh operations is effectively reduced. Inaddition to this leak breaking means, another leak breaking means may beused for breaking down always a leakage of current of another system ofcircuits which remain in an inactive state in a stand-by mode, for thepurpose of a further reduction to the consumption of current.

In accordance with the semiconductor memory device, the leak breakingmeans comprises, for example, a switch circuit inserted into the leakpath and a control circuit for controlling the switch circuit to be inan OFF-state in the interval of time period.

In accordance with this configuration, the control circuit controls theswitch circuit to be in the OFF-state in the interval of time period forbreaking down the leak path, into which this switch circuit is inserted.

Accordingly, a reduction is made to the leakage of current of the systemof circuits associated with the refresh operations in the interval oftime period between the refresh operations.

In accordance with the semiconductor memory device, the switch circuitcomprises, for example, an MOS transistor having a gate thresholdvoltage which is higher than transistors forming the system of circuitsassociated with the refresh operations.

In accordance with this configuration, the MOS transistor forming theswitch circuit inserted into the leak path has the high gate thresholdvoltage for suppressing a sub-threshold current of this MOS transistor,for example. Accordingly, this MOS transistor is placed into theOFF-state in the interval of time period for effectively breaking downthe above-described leak path.

In accordance with the semiconductor memory device, the system ofcircuits associated with the refresh operations receives a reduced powervoltage.

In accordance with this configuration, reduction to the power voltagecauses further reductions to the operating current and the leak currentof the system of circuits associated with the refresh operations.

In accordance with the semiconductor memory device, the system ofcircuits associated with the refresh operations comprise MOS transistorshaving lower gate threshold voltages adopted to the reduced powervoltage.

In accordance with this configuration, it is possible to reduce thepower voltage without reducing the operating speed of the system ofcircuits associated with the refresh operations. Thus, a furtherreduction to the power consumption through the reduction of the powervoltage is available without reducing the operating speed.

In accordance with the semiconductor memory device, the system ofcircuits associated with the refresh operations comprise a transistor,which forms a critical path and has a gate threshold voltage lower thana transistor forming a non-critical path.

In accordance with this configuration, a consumption of current by thecircuit acting as the non-critical path can be reduced without reducingthe operating speed of the circuit acting as the critical path.Accordingly, the consumption of current can be effectively reducedwithout dropping the operating speed apparently.

In accordance with the semiconductor memory device, the leak breakingmeans is configured to delay a chip select signal for generating aninternal chip select signal so as to break down the leak path based onthe internal chip select signal when the chip select signal for switchbetween a stand-by mode and an active mode is transitioned from anactivated state into an inactivated state.

In accordance with this configuration, even if the chip select signal istoggled in a short time period, while the internal chip select signal ismaintained in the active state. Accordingly, the system of circuitscontrolled by this internal chip select signal shows no unnecessaryoperations for avoiding unnecessary operating currents.

BRIEF DESCRIPTIONS OF DRAWINGS

FIG. 1 is a view showing an example of a circuit configuration forreducing a leakage of current in accordance with the prior art.

FIG. 2 is a block diagram schematically showing an entity of a basicconfiguration of a semiconductor memory device in accordance with afirst embodiment of the present invention.

FIG. 3 is a timing chart describing a basic refresh operation of thesemiconductor memory device in accordance with the first embodiment ofthe present invention.

FIG. 4 is a block diagram schematically showing an entity of acharacteristic configuration of the semiconductor memory device inaccordance with the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a control signalcircuit in accordance with the first embodiment of the presentinvention.

FIG. 6 is a block diagram showing a configuration of a control signalgenerating circuit in accordance with the first embodiment of thepresent invention.

FIG. 7 is a timing chart describing processes for generating an internalchip select signal CSI from a chip select signal /CS in accordance withthe first embodiment of the present invention.

FIG. 8 is a timing chart describing processes for generating an internalchip select signal CSI from timer signals TM1, TM2 in accordance withthe first embodiment of the present invention.

FIG. 9 is a block diagram schematically showing a configuration (cellarray block) of a semiconductor memory device in accordance with asecond embodiment of the present invention.

FIG. 10 is a timing chart describing a read operation of thesemiconductor memory device in accordance with the second embodiment ofthe present invention.

FIG. 11 is a view showing a configuration (a power supply circuit and aground supply circuit for a cell array block) of a semiconductor memorydevice in accordance with a third embodiment of the present invention.

DETAILED DESCRIPTION OF VARIOUS EMBODIMENTS

The embodiments of the present invention will, hereinafter, bedescribed.

(First Embodiment)

In accordance with this first embodiment, a semiconductor memory devicecomprises a pseudo-SRAM having a basic configuration of DRAM and beingconfigured to allow an external asynchronous access, wherein thesemiconductor memory device includes a refresh circuit system forautomatically refreshing data stored in memory cells with timingsmatched over plural operation modes. The semiconductor memory devicealso includes a leak breaking means for breaking a leak path between theabove refresh circuit system and either a power source or a ground in aninterval of time period between the refresh operations for the purposeof reducing the consumption of current.

The following descriptions will be made for basic configuration andoperation related to the refresh operations before describingcharacteristic configuration and operation of reducing the leakage ofcurrent of the system of circuits associated with the refreshoperations.

(1) Basic Configuration and Operation in View of Refresh Operation

FIG. 2 schematically shows a whole configuration of a semiconductormemory device in accordance with this embodiment.

FIG. 2 shows the configuration concerning the basic refresh operationsbut not illustrates the configuration of reducing the consumption ofcurrent by the system of circuits associated with the refresh operationsas a characteristic of this embodiment.

In this drawing, an address ADD is a signal externally given andincludes a row address designating a row of a memory cell array to bedescribed later and a column address of a column thereof. A chip selectsignal /CS (“/” representing negative logic) is a most significantcontrol signal for this semiconductor memory device, and switchesbetween a stand-by mode and an active mode. An output enable signal /OEis a control signal for enabling data to be outputted to the outside andfor mainly controlling an active state of a data-out buffer on a finalstage. A write enable signal /WE is a control signal for switchingbetween a write mode and a read mode in an active mode.

An address input system 101 latches the address ADD and outputs aninternal address LADD. An address transition detector circuit (ATD) 102detects a transition of the internal address LADD and outputs a one-shotpulse signal OSP. An address multiplexer (MUX) 103 outputs, as anaddress MADD, selected one of the row address included in the internaladdress LADD and a refresh address RADD to be described below.

A row decoder 106 decodes the address MADD for selecting a row of amemory cell array 107. The memory cell array 107 comprises a matrixarray of memory cells similarly to the general-purpose DRAM. A senseamplifier 171 amplifies a data signal on a bit line for a readoperation. A column decoder 172 selects a column of the memory cellarray 107. Even illustration is not made, the column decoder 172 issupplied with a signal obtained through decoding a column addresscomponent of the internal address LADD outputted from theabove-described address input system 101. A pre-charge circuit (notillustrated) for bit lines is provided accompanying to the senseamplifier 171.

A refresh timer circuit 8G times a refresh time interval. A refreshcontrol circuit 8H controls a series of refresh operations and generatesa refresh control signal REFA for controlling a timing of a refreshoperation accompanying to an external access and a refresh controlsignal REFB for controlling a timing of a self-refresh operation.

A refresh address generator circuit 8J generates an address RADD(hereinafter referred to as “refresh address”) to be used for therefresh operation. An internal pulse generator circuit 10 generates arow enable signal RE, a sense amplifier enable signal SE, a pre-chargeenable signal PE and a column enable signal CE.

Other than the above-described circuits, there are further provided asystem of circuits for controlling read and write operations, anothersystem of circuits for generating a substrate potential of the memorycell array and still another system of circuits for read and writeoperations of data to the memory cell array.

The read and write operations and the refresh operation of thesemiconductor memory device shown in FIG. 2 will, in sequence, bedescribed as the basic operations with reference to a timing chart ofFIG. 3.

A. Read and Write Operations

A read operation according to an address access will be described as oneexample. In this case, a chip select signal /CS and an output enablesignal /OE are set at a low level, while a write enable signal /WE isset at a high level, wherein the address ADD is applied from the outsidein accordance with the specification.

The address ADD is taken through the address input system 101 as theinternal address LADD. Except for the refresh, this internal addressLADD is supplied as the address MADD through the multiplexer 103 to therow decoder 106. At a timing defined by the row enable signal RE, therow decoder 106 selects one word line in the memory cell array 107, sothat data of memory cells connected to this single row of this word lineare read out onto respective bit lines. These data are amplified by thesense amplifier 171 at a timing defined by the sense amplifier enablesignal SE.

On the other hand, based on a column address (not illustrated) includedin the address ADD, and at a timing defined by the column enable signalCE, the column decoder 172 selects a bit line of the memory cell array107, so that data on this bit line are supplied through the data outputcircuit system not illustrated to the outside. Prior to the operation ofreading data from the memory cells, bit lines are pre-charged based onthe pre-charge enable signal PE.

In the above-described series of read operations, upon a transition ofthe internal address LADD, the address transition detector circuit (ATD)102 detects this transition of the internal address LADD and outputs aone-shot pulse signal OSP. By triggering this one-shot pulse signal OSP,the internal pulse generator circuit 109 outputs, at appropriatetimings, the above-described row enable signal RE, the sense amplifierenable signal SE, the pre-charge enable signal PE and the column enablesignal CE.

B. Refresh Operation (In Read Mode)

A refresh operation in a read mode will subsequently be described withreference to a timing chart shown in FIG. 3(a).

In the read mode, the semiconductor memory device shows a sequentialperformance of both the refresh operation and the read operation in thesame cycle in accordance with the specification.

The address input system 101 latches an address A0 given from theoutside as the address ADD and then outputs the internal address LADD.The address transition detector circuit 102 detects a transition of theinternal address LADD and outputs the one-shot pulse signal OSP.

Upon receipt of the one-shot pulse signal OSP, the refresh controlcircuit 108H starts the refresh operation. Upon the start of the refreshoperation, the refresh address generator circuit 108J generates andoutputs a refresh row address R0 as the refresh address RADD. Under thecontrol of the refresh control circuit 108H, the address multiplexer 103supplies the refresh address RADD (the refresh row address R0) as theaddress MADD to the row decoder 106.

On the other hand, the internal pulse generator circuit 109 receives aninput of the refresh control signal REFB from the refresh controlcircuit 108H, and outputs the row enable signal RE and the senseamplifier enable signal SE. The row decoder 106 receives inputs of theaddress MADD and the row enable signal RE and selects a word linedesignated by the refresh address R0 for a predetermined time perioddefined by the row enable signal RE. Data signals of the memory cellsconnected to the selected word line are amplified by the senseamplifiers 171 and then re-stored therein, whereby the data of thememory cells for the single row designated by the refresh address R0have been refreshed.

After the refresh operation has been finished for the row designated bythe refresh row address R0, then the read operation is made in the samecycle. For example, the address multiplexer 103 receives the internaladdress LADD from the address input system 101 and supplies the internaladdress LADD as the address MADD to the row decoder 106. The row decoder106 selects the word line designated by the row address X0 entered asthe input address MADD. The sense amplifier 171 amplifies the datasignal appearing on the bit line in the memory cell array 107 forreading out the data stored in the memory cell.

C. Refresh Operation (In Stand-by Mode)

A refresh operation in a stand-by mode will be described with referenceto a timing chart shown in FIG. 3(b).

In the stand-by mode, the refresh control circuit 108H times a past timefrom a time of the last external request for access, so that if the pasttime becomes beyond a predetermined refresh time, then the refreshcontrol circuit 108H outputs the refresh control signal REFB to startthe self-refresh operation.

In the stand-by mode, for example, the refresh timer circuit 108G timesa time interval for self-refresh operations. The refresh control circuit108H controls the refresh address generator circuit 108J to generate therefresh row address R0 as the refresh address RADD at a timing obtainedby the timing operation of the refresh timer circuit 108G. The addressmultiplexer 103 receives an input of the refresh row address R0 as therefresh address RADD and supplies it as the address MADD to the rowdecoder 106.

On the other hand, the refresh control circuit 108H outputs the refreshcontrol signal REFB to cause the internal pulse generator circuit 109 togenerate the row enable signal RE at the appropriate timing. The rowdecoder 106 receives the input of the refresh row address R0 as theaddress MADD from the address multiplexer 103 and also selects a wordline designated by the refresh row address R0 for a predetermined timeperiod at a timing defined by the row enable signal RE. Data stored inthe memory cells connected to the selected word line are amplified bythe sense amplifier 171 similarly to the above described read mode andthen re-stored in the original memory cells. Thereafter, in the stand-bymode, the refresh operations will be executed for the rows defined bythe refresh addresses sequentially generated by the refresh addressgenerator circuit 108J in accordance with timings generated by therefresh timer circuit 108G.

As described above, a voluntarily refresh (self-refresh) is executedwith timings matched over the read mode and the stand-by mode. Inaccordance with the above-described example, the descriptions have beenmade for the read mode. In the write mode, the refresh is voluntarilyexecuted with timings matched over the write mode and the stand-by mode.The refresh timings are matched over the read mode and the write mode.Namely, the refresh is executed independently from the operation modes.Matching the timings of the refresh over the plural operation modesallows the asynchronous access to the semiconductor memory devicewithout taking into account the refresh from the outside.

(2) Characteristic Configuration and Operation for Reducing theConsumption of Current

The characteristic configuration and operation for reducing theconsumption of current in accordance with this embodiment will bedescribed.

As described above, the semiconductor memory device is configured toperform the self-refresh independently from the active mode and thestand-by mode, for which reason as long as the self-refresh operation isconcerned, in any operation modes, the interval of time period betweenthe refresh operations is present. In this interval of time period, theleakage of current is caused. On the specification, the operation modewith appearance of the considerable leakage of current of this type isthe stand-by mode. Accordingly, in accordance with this firstembodiment, effective suppression to the leakage of current in theinterval of time period between the self-refresh operations in thestand-by mode will be described as an example.

FIG. 4 schematically shows the configuration of the semiconductor memorydevice in accordance with this embodiment by attracting the function ofreducing the consumption of current by the system of circuits associatedwith the refresh operations. In this drawing, the code 1 represents acell array block comprising a matrix array of memory cells, wherein thecell array block 1 corresponds to the memory cell array 107 shown inFIG. 2. This cell array block 1 comprises the number “n” of dividedblocks 1−n (n: the natural number not less than 2). In this example, thecell array block is divided into plural blocks, but this is optional.

The code 2 represents a control signal circuit which receives inputs ofan address Add (corresponding to the address ADD shown in FIG. 2) and achip select signal /CS. The control signal circuit 2 generates aninternal address signal M-Add, a sense amplifier enable signal SE, apre-charge signal PC, and an internal chip select signal CSI to bedescribed later. This control signal circuit 2 is configured to have afunction of generating the internal chip select signal CSI, in additionto the same functions of the address input system 101, the addresstransition detector circuit 102, the multiplexer 103, the refresh timercircuit 108G, the refresh control circuit 108H, the refresh addressgenerator circuit 108J and the internal pulse generator circuit 109.Detailed configurations of this control signal circuit 2 will bedescribed later.

The internal address signal M-Add includes the above-described addressMADD and the above-described refresh address RADD shown in FIG. 2 aswell as a block selecting signal. The pre-charge signal PC correspondsto the pre-charge enable signal PE shown in this drawing. The pre-chargesignal PC is a control signal for pre-charging bit lines and data linesin the cell array block. The internal chip select signal CSI becomes lowlevel in the interval of time period between refresh operations in thestand-by mode. The internal chip select signal CSI is a control signalfor breaking down the leak path in the interval of time period. Asdescribed below, the internal chip select signal CSI is generated fromthe chip select signal /CS externally supplied. The internal chip selectsignal CSI has an inverted logic value to the chip select signal /CS,provided that the internal chip select signal CSI is forciblytransitioned into the high level during the refresh operation.

The internal address signal M-Add, the sense amplifier enable signal SE,and the pre-charge signal PC are supplied to the cell array block 1together with an Y-address (column address) included in the internaladdress LADD. A part of this Y-address is used for selecting a column ofthe cell array block 1. The remaining parts of the Y-address are usedfor selecting the blocks 1˜n. In this example, the Y-address isgenerated by the different system of circuits from the control signalcircuit 2. It is also possible that the Y-address is generated by thecontrol signal circuit 2.

The code 3 represents an interval voltage-down circuit for generating areduced internal voltage VINT. A reference voltage Vref1 lower involtage than an external power voltage is compared to the internalvoltage VINT by a comparator 3A, so that a current to be suppliedthrough a p-channel transistor 3B is controlled in accordance with adifference between them, thereby reducing the external power voltage forgenerating the internal voltage VINT. An n-channel transistor 3Csupplies the ground voltage to the comparator 3A. The n-channeltransistor 3C acts as a switch circuit for breaking down the leak pathbetween the comparator 3A and the ground.

The code 4 represents a boost circuit for generating a boost voltage VBBproviding a potential to the word line and a substrate voltage BBG inthe cell array block 1. The boost circuit 4 comprises a comparator 4A,an n-channel transistor 4B, a ring oscillator 4C and a charge pump 4D.The n-channel transistor 4B supplies the ground level to the comparator4A The n-channel transistor 4B acts as a switch circuit for breakingdown the leak path between the comparator 4A and the ground. Inaccordance with this boost circuit 4, the comparator 4A compares thesubstrate voltage BBG to a reference voltage Vref2 for causing thesubstrate voltage BBG to be equal to this reference voltage. The ringoscillator 4C oscillates at a predetermined frequency based on a powerof the output from the comparator 4A. The boost voltage VBB boosted fromthe oscillated output is then outputted from the charge pump 4D. Thecomparators provided in the above-described internal voltage-downcircuit 3 and the boost circuit 4 do not function and are placed in theinactive state in the stand-by mode. In the stand-by mode, however, thep-channel transistor 3B, the charge pump 4D and the ring oscillator 4Care controlled in the active state for continuing the supplies of theboost voltage VBB and the substrate voltage BBG.

FIG. 5 shows the detailed configuration of the control signal circuit 2.

In this drawing, the code 201 represents an input buffer which receivesan input of the address Add. The input buffer 201 corresponds to theaddress input system 101 shown in FIG. 2. The code 202 represents aninput buffer which receives an input of the chip select signal /CS. Thecode 203 represents an address transition detector circuit whichcorresponds to the address transition detector circuit 102. The code 204represents an inverter, while the code 205 represents a NAND-gate. Theinverter 204 and the NAND-gate 205 form a gate circuit for inactivatingthe output signal (one shot pulse) from the address transition detectorcircuit 203 in the stand-by state. The NAND-gate 205 performs aNAND-operation of the output signal (one shot pulse) from the addresstransition detector circuit 203 and the chip select signal /CS so as tooutput a one-shot pulse signal AO.

The code 206 represents a multiplexer which corresponds to the addressmultiplexer 103 shown in FIG. 2. The code 207 represents a timercircuit. The code 208 represents a timing signal generator circuit. Thetimer circuit 207 and the timing signal generator circuit 208 correspondto the refresh timer circuit 108G shown in FIG. 2. The timing signalgenerator circuit 208 outputs the one-shot pulse signal RO at a cycledefined by a timer signal TM2. The code 209 represents a refresh addresscounter which corresponds to the refresh address generator circuit 108Jshown in FIG. 2.

The code 210 represents a CSI generator circuit which generates theabove-described internal chip select signal CSI. The code 211 representsa control signal generator circuit which corresponds to the refreshcontrol circuit 108H and the internal pulse generator circuit 109 shownin FIG. 2. This control signal generator circuit 211 generates andoutputs the sense amplifier enable signal SE and the pre-charge signalPC from the one-shot pulse signals AO, RO and the internal chip selectsignal CSI.

The above-described timer circuit 207 comprises a ring oscillator 207A,an inverter chain 207B, and a NOR-gate 207C. The ring oscillator 207Agenerates a timer signal TM1 having a predetermined clock cycle. Theinverter chain 207B delays the timer signal TM1 and generates the timersignal TM2. The NOR-gate 207C performs the NOR-operation of the timersignals TM1 and TM2 to generate a signal PT.

The above-described CSI generator circuit 210 comprises an inverterchain 210A, a NAND-gate 210B, a transfer gate 210C, an inverter 210D anda p-channel transistor 210E. The inverter chain 210A and the NAND-gate210B function as a delay circuit for delaying the high level of the chipselect signal /CS. The transfer gate 210C, the inverter 210D and thep-channel transistor 210E function as a gate for forcibly causing theinternal chip select signal CSI to be transitioned into the high level,based ion the signal PT outputted from the timer circuit 207.

FIG. 6 shows an example of the configuration of the above-describedcontrol signal generator circuit 211.

Even the one-shot pulse signals AO, RO as the input signals areillustrated in combination in FIG. 6, the control signal generatorcircuit shown in FIG. 6 is provided for each of those one-shot pulsesignals AO, RO, to generate the sense amplifier enable signal SE and thepre-charge signal PC. The code 30 represents a signal generator circuitfor generating the sense amplifier enable signal SE and the pre-chargesignal PC from the one-shot pulse signals AO, RO. The code 31 representsan n-channel transistor inserted into between the ground and the signalgenerator circuit 30. The code 32 represents an inverter. The code 33represents a p-channel transistor inserted into between the power supplyand the signal generator circuit 30.

A gate of the n-channel transistor 31 is supplied with the internal chipselect signal CSI. A gate of the p-channel transistor 33 is suppliedwith an inversion signal inverted by the inverter 32 from the internalchip select signal CSI. The n-channel transistor 31 and the p-channeltransistor 33 show concurrent switching operations of ON and OFF. Gatethreshold voltages of the n-channel transistor 31 and the p-channeltransistor 33 are set higher than the gate threshold voltage of the MOStransistors forming the signal generator circuit 30 so as to effectivelysuppress the sub-threshold current.

The signal generator circuit 30comprises inverters 30A, 30B, 30C, anNAND-gate 30D and an inverter 30E, all of which have CMOS configuration.One input of the NAND-gate 30D is supplied with the one-shot pulsesignals AO, RO. Another input of the NAND-gate 30D is supplied with theabove-described one-shot pulse signals AO, RO which have beentransferred through the inverter chain (delay path) comprising theinverters 30A and 30C. An output from the NAND-gate 30D is supplied tothe inverter 30E. An output from the inverter 30E is the sense amplifierenable signal SE and the pre-charge signal PC. The inverters 30A and 30Cand the NAND-gate 30D are supplied with the ground through the n-channeltransistor 31, while the inverters 30B and 30E are supplied with thepower through the p-channel transistor 33.

The characteristic configuration in accordance with this firstembodiment has been described.

The characteristic operations in this first embodiment, namely theoperation (leak breaking down operation) of breaking down the leakage ofcurrent generated in the interval of time period between theself-refresh operations in the stand-by mode will, hereinafter, bedescribed.

This operations are made based on the above-described internal chipselect signal CSI. Process for generating the internal chip selectsignal CSI and the technical sense of this signal will be describedbefore descriptions of the leak breaking down operation.

The process for generating the internal chip select signal CSI based onthe chip select signal /CS will be described with reference to FIG. 7.

As shown in FIG. 7, at a time t1, the chip select signal /CS istransitioned into the low level (in other words, the chip select signalCS is transitioned to the high level), whereby the operation mode of thesemiconductor memory device becomes the active mode. In the CSIgenerator circuit 210 shown in FIG. 5, the inversion signal from thechip select signal /CS is outputted as the internal chip select signalCSI with by-passing the inverter chain 210A at a time t2 which isimmediately after the time t1.

Upon this chip select signal /CS, in a period of time defined from atime 3 to a time t4, the one-shot pulse signals AO, RO of the high levelare outputted from the NAND-gate 205 and the timing signal generatorcircuit 208, respectively.

Upon the one-shot pulse signals AO, RO, the signal generator circuit 30shown in FIG. 6 is operated to output the sense amplifier enable signalSE and the pre-charge signal PC. For example, the signal generatorcircuit 30 outputs the high level pulse signals of the sense amplifierenable signal SE and the pre-charge signal PC because both inputs intothe NAND-gate 30D are in the high level during a period of time, whereinboth the input and output signals of the delay circuit comprising theinverters 30A˜30C are in the high level, provided that the period oftime is namely defined from the time t3 of transitions of the one-shotpulse signals AO, RO from the low level to the high level and until atime has been past which corresponds to the delay time of the inverterchain.

At a time t5, he chip select signal /CS is transitioned to the highlevel (in order words, the chip select signal CS is transitioned intothe low level), whereby the operation mode becomes the stand-by mode. Inthe CSI generator circuit 210 shown in FIG. 5, the inversion signal fromthe chip select signal /CS is delayed by the inverter chain 210A,whereby the sense amplifier enable signal SE and the pre-charge signalPC are outputted with a delay. As a result, in FIG. 7, the internal chipselect signal CSI is transitioned gain to the low level at a time t6which is later than the time t5 by the delay time of the above-describedinverter chain 210A.

As described above, the internal chip select signal CSI is promptlytransitioned into the high level for transition into the active mode. Atthe same time when the operation mode becomes the active mode, a systemof circuits receiving the input of the internal chip select signal (forexample, the internal voltage down circuit 3 and the boost circuit 4) iscontrolled in the operable state. In contrast, if the operation modebecomes the stand-by mode (namely the chip select signal /CS istransitioned from the active state to the inactive state), the chipselect signal /CS is delayed to generate the internal chip select signalCSI. The internal chip select signal CSI is transitioned into the lowlevel with a delay of a predetermined time, thereby breaking down theleak path. The reason why the internal chip select signal CSI is delayedfor transition of the operation mode from the active mode into thestand-by mode would be to maintain the internal chip select signal CSIin the high level (in the active state) when the chip select signal /CSis toggled at a short cycle, for the purpose of suppressing anyunnecessary operation current of the circuit system which receives theinput of the internal chip select signal CSI.

The process for generating the internal chip select signal CSI based onthe timer signals TM1 and TM2 in the stand-by mode will be describedwith reference to FIG. 8.

In the initial state, the chip select signal /CS is in the high level,and the operation mode is the stand-by mode. Prior to a time t10, uponreceipt of the high level of the chip select signal /CS, the NAND-gate210B outputs the low level of the internal chip select signal CSI. Asdescribed later, the internal chip select signal CSI is in the low levelin the interval of time period between the refresh operations, andfunctions of breaking the leak path of the system of circuits associatedwith the refresh operations.

At the time t10, the ring oscillator 207A outputs the timer signal TM1which is transitioned to the high level, upon which the refreshoperation is started, and the NOR-gate 207A outputs the low level of thesignal PT. Upon receipt of this signal PT, the p-channel transistor 210Eturns ON, while the transfer gate 210C turns OFF, whereby at a time t11,the internal chip select signal CSI is transitioned to the high level.

On the other hand, the timer signal TM1 is delayed by the inverter chain207B and then outputted as the timer signal TM2 from the timer circuit207 at a time t12. Upon receipt of this timer signal TM2, the timingsignal generator circuit 208 outputs the high level of the one-shotpulse signal RO at a time t13. This one-shot pulse signal RO is inputtedinto the multiplexer 206, the refresh address counter 209 and thecontrol signal generator circuit 211 thereby executing a series of therefresh operations.

The one-shot pulse signal RO is delayed by the inverter chain 207B andthen transitioned to the high level after the transition of the internalchip select signal CSI. Namely, the internal chip select signal CSI istransitioned into the high level by the timer signal TM1 before thetransition of the one-shot pulse signal RO, thereby breaking down theleak path of the system of circuits associated with the refreshoperations such as the power system and the control system, prior to therefresh operation is executed. Even if those circuits are in theinoperable state (in non-responsible state to the input signal), then itis possible to activate previously operations of the power system andthe control system before the internal operations for refresh (selectingword and activating sense amplifier) are started. Accordingly, it ispossible to perform the refresh operation without any trouble even ifthe leak path of the system of circuits associated with the refreshoperation remains broken down.

At a time t14, the timer signal TM1 is transitioned to the low level,whereby at a time t16, the timer signal TM2 is transitioned to the lowlevel, while the signal PT is transitioned to the high level. Uponreceipt of this signal PT, the p-channel transistor 210E turns OFF,while the transfer gate 210C turns ON, resulting in that at a time t17,the internal chip select signal CSI is transitioned to the low level.The transition of the internal chip select signal CSI into the low levelcauses that the leak path of the system of circuits receiving the inputof the internal chip select signal CSI is broken down. The one-shotpulse signal RO is transitioned to the low level at a time t15 which islater by a predetermined time period from the time t13, whereby theinternal operations based on the one-shot pulse signal RO have beencompleted before a time t17 when the internal chip select signal CSI istransitioned to the low level.

As described above, the internal chip select signal CSI provides for atime period, in which the system of circuits associated with the refreshoperation is in the operable state. Namely, the internal chip selectsignal CSI provides for another time period, for example, the intervalof time period between the refresh operations, in which the system ofcircuits associated with the refresh operation is in the inoperablestate. In this point of view, in accordance with the first embodiment,the internal chip select signal CSI services as a control signal forbreaking down the leak path of the system of circuits associated withthe refresh operation by triggering the timer, in the interval of timeperiod between the refresh operations.

The process for generating the internal chip select signal CSI and thesignificance of this signal have been described above.

Descriptions will be made with reference to FIGS. 4 and 6 for the leakbreaking down operation based on the internal chip select signal CSI.

In the configuration shown in FIG. 4, the comparators 3A and 4A arefixed in a static operation state in the stand-by mode. Namely, in thestand-by mode, the comparators 3A and 4A are in the operation state butin the static operation state, wherein the internal signals are notdynamically transitions. The comparators 3A and 4A are configured sothat the supply of the ground potential is not needed for maintainingthis static operation mode. In this case, in the inside of thecomparators 3A and 4A, the leak path provides a connection between thepower supply and the ground, whereon the n-channel transistors 3C and 4Bare inserted onto the leak path.

In this state, the internal chip select signal CSI is transitioned tothe low level in the refresh interval of time period. The n-channeltransistors 3C and 4B with the gates which receive the internal chipselect signal CSI will turn OFF, whereby the leak paths between thecomparators 3A and 4A and the ground are broken down to prevent the leakcurrent of the comparators 3A and 4A. Since the gate threshold voltageof the n-channel transistor 3C is set higher than the gate thresholdvoltage of the MOS transistors forming the comparators 3A and 4A, thesub-threshold current in the OFF-state is suppressed. Accordingly, theleakage of current between the comparators 3A and 4A and the ground iseffectively suppressed.

The leak breaking down operation will be described with reference toFIG. 6.

In this drawing, the one-shot pulse signals AO, RO are in the low level.In this state, in the inside of the CMOS-configured inverters 30A, 30Cand the NAND-gate 30D, the n-channel transistors are in the OFF-state.In the inside of the inverters 30B and 30E, the p-channel transistorsare in the OFF-state. The gate threshold voltages of those MOStransistors being in the OFF-state are set low so that the sub-thresholdcurrents of those transistors are relatively large so remarkable as theleakage of current.

The internal chip select signal CSI is transitioned to the low level,whereby the n-channel transistor 31 turns OFF, whereby the leak pathsbetween the inverters 30A, 30C and the NAND-gate 30D and the ground arebroken down. Since the gate threshold voltage of the n-channel MOStransistor 31 is set so high as suppressing the sub-threshold current,the leakage of current flowing through the n-channel transistors of theabove-described inverters 30A, 30C and the NAND-gate 30D is suppressedby the n-channel transistor 31. Similarly, the internal chip selectsignal CSI is transitioned to the low level, whereby the p-channeltransistor 33 having the high gate threshold voltage turns OFF, therebyto effectively suppress the leakage of current between the inverters 30Band 30E and the power supply.

The leak break down operations have been described.

As described above, in accordance with the semiconductor memory deviceof this first embodiment, the leak path of the system of circuitsassociated with the refresh operations is broken down in the interval oftime period between the refresh operations which are discontinuouslyexecuted. At this time, the state of the internal signals of the systemof circuits associated with the refresh operations is identical with thestate that the leak path is not brown down. In this point of view, thecircuit state is kept in the same state as supplying the power.Accordingly, in accordance with this embodiment, the current suppressionis caused without discontinuation of the power supply.

In addition, in this first embodiment, the leak path is broken down withsupplying the power (power or ground) necessary for maintaining thesignal state in the inside of the circuit, whereby the leakage ofcurrent can effectively be suppressed in the interval of time period,with keeping the original signal state in the interval of time period.Accordingly, the technical concept of breaking the leakage of current inaccordance with this embodiment is different from the conventionalmeasure of breaking the power supply to reduce the consumption ofcurrent.

As described above, in accordance with the first embodiment, the leakpath of the system of circuits associated with the refresh operations isbroken down in the interval of time period between the refreshoperations for effectively reducing the consumption of current in thestand-by mode.

The two different timer signals TM1 and TM2, on of which is delayed fromanother, are used to generate the internal chip select signal CSI, basedon which the leak path is broken down in the interval of time period, sothat the leak path once broken will promptly be recovered before therefresh operations. Accordingly, at the transition from the interval oftime period to the refresh operation, the system of circuits with thebroken leak path can be recovered to the operable state for promptexecution of the refresh operation.

In this first embodiment, the leak path is broken down which was formedin the interval of time period in the stand-by mode. This is optional.The technical concept of the present invention is applicable to anytypes of the refresh, for example, the self-refresh to be executed bytriggering the timer generated if no address transition is caused in apredetermined period of time in the active mode.

(Second Embodiment)

The second embodiment of the present invention will be describedhereinafter.

In accordance with this second embodiment, in addition to theabove-described configuration of the first embodiment, a gate thresholdvoltage of transistors forming a critical path is set lower than a gatethreshold voltage of transistors forming a non-critical path. FIG. 9shows an example of the characteristic configuration of thesemiconductor memory device in accordance with the second embodiment.

This example shown in the drawing includes memory cells and thoseperipheral circuits. In this drawing, a MOS transistor encompassed by acircle mark is a transistor having a high gate threshold voltage. Thecode MC represents memory cells aligned in matrix and being connectedbit lines B, /B running in a column direction, and word lines WL runningin a row direction. Each of the memory cells MC comprises a singletransistor and a single capacitor, wherein one electrode of thecapacitor is fixed at a voltage HVDD.

The code 300 represents a word line driver which comprises n-channeltransistors 300A, 300D and n-channel transistors 300B, 300C and 300E.The word line driver 300 is selected by a row address RA and a main wordline MWL for driving a word line WL. This diver 300 has a function of anAND-gate. The code 301 represents a main word line driver whichcomprises p-channel transistors 301A, 301B and n-channel transistors301C, 301D. The main word line driver 301 is selected by a blockselecting signal /Block and a main word line selecting signal /Main fordriving a main word line MWL. This driver 301 has a function of anNOR-gate.

The code 302 represents a bit line pre-charge circuit, which comprisesn-channel transistors 302A˜302C. The n-channel transistor 301A isprovided for unifying potentials of the bit lines B, /B. The n-channeltransistors 302B, 302C is provided for charging up the bit line at thevoltage HVDD. The code 303 represents a driver for outputting apre-charge enable signal PE. The driver 303 comprises p-channeltransistors 303A and 303C and n-channel transistors 303B, 303D and 303E.This driver 303 has a function of an AND-gate. The code 304 represents alatch-type sense amplifier which comprises a flip-flop, which comprisesa cross-connected paired CMOS inverters supplied with sense amplifiercontrol signals SAP and NAP as power and ground.

The code 305 represents a driver for outputting the sense amplifiercontrol signal SAP. The driver 305 comprises p-channel transistors 305A,305B, 305E and n-channel transistors 305C and 305D. This driver 305 hasa function of an AND-gate which outputs the high level in the activestate. The code 306 represents a driver for outputting the senseamplifier control signal NAP. The driver 306 comprises p-channeltransistors 306A and 306C, and n-channel transistors 306C, 306D and306E. This driver 306 has a function of an OR-gate outputting the lowlevel in the active state.

A transfer gate 307 comprises n-channel transistors 307A and 307B whichconnects a single pair of bit lines B, /B to another single pair of datalines BUS. The transfer gate 307 serves as a switch selecting the bitlines. The code 309 represents a driver for outputting a row address RA.The driver 309 comprises p-channel transistors 309A, 309B and n-channeltransistors 309C and 309D. This driver 309 has a function of a NOR-gate.

The operations of the circuits shown in FIG. 9 will be described byattracting a critical path with reference to FIG. 10.

The operations of reading out data from the memory cells MC shown inFIG. 9 may comprise the following operations:

(a) operation of pre-charging bit lines B, /B;

(b) operation of selecting a memory cell MC;

(c) operation of activating a sense amplifier to amplify data signal onthe bit lines ; and

(d) operation of rendering conductive MOS transistors 307A and 307Bforming a column switch.

Those operations should be executed time-sequentially for satisfying thepredetermined timings, for which reason each of those operations has acritical path.

In FIG. 10, at a time t20, the block selecting signal /Block inputted tothe driver 301 is transitioned to the low level. At a time t22, the mainword line selecting signal Main is transitioned to the high level (/Mainof FIG. 9 is transitioned to the low level), whereby the main word lineMWL is driven to the high level. At a time t20, the block selectingsignal /Block inputted to the driver 309 is transitioned to the lowlevel and the row address signal /X-RA is transitioned to the low level,whereby at a time t23, the row address RA is driven to the high level.Upon the main word line MWL and he row address RA being driven to thehigh level, the driver 300 drives the word line WL to the high level,whereby the memory cell MC is selected for causing stored data to be onthe bit lines B, /B.

At a time t24, the sense amplifier enable signal SE is transitioned tothe high level at a predetermined timing, whereby the driver 305 drivesthe sense amplifier control signal SAP to the high level. At the sametime t24, the sense amplifier enable signal /SE shown in FIG. 9 istransitioned to the low level, whereby the driver 306 drives the senseamplifier control signal SAN into the low level. As a result, the senseamplifier 304 is activated to amplify the data on the bit lines B, /B.At a time t21, the block selecting signal Block is transitioned to thelow level, while the block selecting signal /Block is transitioned tothe high level, whereby the read operation from the memory cell isfinished.

An investigation will, hereinafter, be made for the MOS transistorproviding the critical path. The critical path comprises the MOStransistors supplied with the signal level which defines the timings ofthe internal operation, while the non-critical path comprises the MOStransistor supplied with the signal level having already been defined.

(a) Critical Path to Operation of Selecting Memory Cell

The drivers 300, 301 and 309 are associated with this operation. In FIG.10, the block selecting signal Block has been defined before the mainword selecting signal Main, for which reason the p-channel transistor301A in the driver 301 forms no critical path, wherein the p-channeltransistor 301A receives the block selecting signal /Block and drivesthe main word line MWL to the high level.

In the driver 309, the p-channel transistor 309A forms no critical path,wherein the p-channel transistor 309A receives the block selectingsignal /Block and drives the row address RA to the high level. In thedriver 300, the n-channel transistor 300C driven by the main word limeMWL and the p-channel transistor 300D with the gate driven by thisn-channel transistor 300C form no critical path.

(b) Critical Path to Operation of Pre-Charging Bit Line

The driver 303 is associated with this operation. In FIG. 10, the blockselecting signal Block has been defined before the pre-charge signal PC,for which reason in the driver 303, the n-channel transistor 303Ereceiving the input of the block selecting signal Block and thep-channel transistor 303A with the gate driven by the n-channeltransistor 303E form no critical path.

(c) Critical Path to Operation of Activating Sense Amplifier to AmplifyData

The drivers 305 and 306 are associated with this operation. In thedriver 305, the n-channel transistor 305D receiving the input of theblock selecting signal Block and the p-channel transistor 305E with thegate driven by the n-channel transistor 305D form no critical path. Inthe driver 306, the p-channel transistor 306A receiving the input of theblock selecting signal /Block and the n-channel transistor 306E with thegate driven by the p-channel transistor 306A form no critical path.

(d) Critical Path to Operation of Rendering Conductive Column Switch

The driver 308 is associated with this operation. In the driver 308, then-channel transistor 308C receiving the input of the block selectingsignal Block and the p-channel transistor 308D with the gate driven bythe n-channel transistor 308C form no critical path.

In accordance with this second embodiment, the MOS transistors formingthe non-critical path have high gate threshold voltages, while the MOStransistors forming the critical path have low gate threshold voltages.This configuration allows an effective reduction to the leakage ofcurrent without reducing the operation speed. A large number of thedriver leak paths are broken down to effectively reduce the leakage ofcurrent.

(Third Embodiment)

The third embodiment will be described hereinafter.

In this third embodiment, a power circuit in the cell array block 1shown in FIG. 4 in the above-described first embodiment is controlled bythe internal chip select signal CSI in order to reduce the leakage ofcurrent of the cell array block 1.

The cell array block 1 has a large number of drivers for selectingmemory cells for executing the refresh operations, for which reason thecell array block 1 is involved into the system of circuits associatedwith the refresh operations.

As shown in FIG. 11, in this third embodiment, a power supply circuitfor supplying the power HVD to the above-described driver 300 shown inFIG. 9 comprises a diode 401, a p-channel transistor 402, and aCMOS-configured inverter 403. A gate threshold voltage of MOStransistors forming the p-channel transistor 402 and the inverter 403 isset higher than a gate threshold voltage of the MOS transistors formingthe driver 300. A ground supply circuit for supplying the ground voltageto the driver 300 comprises a diode 404 and an n-channel transistor 405having a high gate threshold voltage.

An anode of the diode 401 is connected to the power supply, while acathode thereof is connected to the power line (HVDD). A source of thep-channel transistor 402 is connected to the power supply, while a drainthereof is connected to the power line (HVDD). The internal chip selectsignal CSI is inverted by the inverter 403 and then supplied to the gateof the p-channel transistor 402.

An anode of the diode 404 is connected to a ground line (VBBL), while acathode thereof is connected to the ground. A source of the n-channeltransistor 405 is connected to the ground, while a drain thereof isconnected to the ground line (VBBL). The internal chip select signal CSIis supplied to the gate of the n-channel transistor 405. In FIG. 11,only one of the driver 300 is shown. Notwithstanding, the same number ofthis driver as the number of the blocks are provided which are commonlyconnected to the same power line (VBBH) and the same ground line (VBBL),wherein those drivers are provided for every rows corresponding to theword lines.

The following descriptions will concern the operations of thisembodiment.

If the internal chip select signal CSI is in the high level, and theoperation state is the refresh operation state in the stand-by mode,then the low level is supplied to the gate of the p-channel transistor402, whereby this transistor turns ON. The high level of the internalchip select signal CSI is supplied to the gate of the n-channeltransistor 405, whereby this transistor also turns ON. Accordingly, thepower voltage and the ground voltage are supplied to the driver 300through the p-channel transistor 402 and the n-channel transistor 405,whereby this driver is driven.

In contrast, if the internal chip select signal CSI is in the low level,and the operation state is in the interval between the refreshoperations, then the p-channel transistor 402 and the n-channeltransistor 405 turn OFF. In this case, the power VBBH is clamped at apotential which is lower than the power potential by a barrier potentialVf of the diode 401. The ground VBBL is clamped at a potential which ishigher than the ground potential by a barrier potential Vf of the diode404.

The power VBBH and the ground VBBL are clamped to prevent any generationof operation currents due to noises such as power bump and coupling,thereby preventing any charge/discharge currents due to noises for veryrefresh operations. This also stabilizes the potentials of the internalnodes of the driver 300 for preventing any erroneous selections to theword lines.

If the internal chip select signal CSI is in the low level, then thep-channel transistor 402 and the n-channel transistor 405 turn OFF.Since, however, the gate threshold voltages of those transistors are sethigh to suppress the sub-threshold current of those transistors foreffectively breaking down the leak paths between the driver 300 in thecell array block and the power and ground. Accordingly, the leakage ofcurrent of this driver 300 is effectively reduced.

In accordance with this third embodiment, the leak path between the cellarray block which generates a large leakage of current and the power andground is broken down, resulting in an extremely effective reduction tothe leakage of current of the system of circuits associated with therefresh operations.

Potentials of the power line and the ground line are clamped by thediodes for stabilizing the state of the circuits even the leak path isbroken down, resulting in no generation of the unnecessary operationcurrents and no malfunctions.

The first through third embodiments of the present invention have beendescribed above. The present invention should not be limited to thoseembodiments, but includes any design change in the context of thesubject of the present invention.

For example, in accordance with the above-described configuration shownin FIG. 6 of the first embodiment, the leak paths of the NAND-gate 30Dand the inverter 30E are broken down in addition to the delay circuit(inverter chain) comprising the inverters 30A˜30C. There is no need ofthe limitation to this configuration. It is also possible that the leakpaths of the inverters 30A˜30C only which form the delay circuit arebroken down, thereby effectively reducing the leakage of current of theinverter chain having a number of the leak paths. This configurationalso reduces the load to the internal chip select signal CSI, therebymaking it easy to ensure the timing margins over the control.

In accordance with the above-described configuration shown in FIG. 4 ofthe first embodiment, the leak paths of the comparators 3A, and 4A arebroken down by the n-channel transistors 3C, 4B. It is not unnecessaryto limit the configuration to this. For example, it is possible to leavea small leak path in order to reduce the power of those comparators butnot to zero. For example, in parallel to the n-channel transistor 3C, ann-channel transistor is provided which generates a larger leakage ofcurrent by about ten times than the leakage of current (sub-thresholdcurrent) of this transistor.

The formation of the reduced leak path reduces the leakage of currentand stabilizes the operations of the comparators in case of the shortinterval time period. The above-described small leak path (for example,leak path higher by ten times than a leakage of current of the n-channeltransistor 3C) may be formed by applying an intermediate voltage to agate of the n-channel transistor which is connected in parallel to then-channel transistor 3C.

Needless to say, the semiconductor memory device in accordance with eachof the above-described embodiments may be formed on a single chip. It isalso possible to realize the device in the form of hybrid IC (integratedcircuit), wherein the circuit comprises plural function blocks, each ofwhich is formed on each separate chip. The technical concept of thisinvention may include such a configuration that a memory chip issupplied with a variety of control signals from a control chip providedoutside the memory chip.

INDUSTRIAL APPLICABILITY

In accordance with this invention, the following effects can beobtained.

Namely, the leak breaking means is provided for breaking the leak pathbetween the system of circuits associated with the refresh operationsand either the power source or the ground in the interval of time periodof the refresh operations, thereby effectively reducing the consumptionof current by the system of circuits associated with the refreshoperations.

The leak breaking means comprises the switch circuit inserted into theleak path and the control circuit for controlling the switch circuit tobe in the OFF-state in the interval of time period, thereby breakingdown the leak path between the system of circuits associated with therefresh operations and either the power source or the ground in theinterval of time period.

The switch circuit comprises the MOS transistor having the gatethreshold voltage which is higher than transistors forming the system ofcircuits associated with the refresh operations for effectively breakingdown the leak path.

The system of circuits associated with the refresh operations receives areduced power voltage for effective reductions to the consumption ofcurrent including an operating current by this system of circuits.

The system of circuits associated with the refresh operations compriseMOS transistors having lower gate threshold voltages adopted to thereduced power voltage in order to reduce the power voltage withoutreducing the operating speed of this system of circuits.

The system of circuits associated with the refresh operations comprise atransistor, which forms a critical path and has a high gate thresholdvoltage for reducing the leakage of current without reducing theoperating speed of this system of circuits.

Other embodiments of the invention will be apparent to those skilled inthe art from a consideration of the specification or practice of theinvention disclosed herein. It is intended that the specification andexamples be considered as exemplary only, with the true scope and spiritof the invention being indicated by the following claims.

1. A semiconductor memory device configured to automatically refreshdata stored in memory cells and to allow an external asynchronousaccess, said device including: a switch circuit inserted into a leakpath between a system of circuits associated with refresh operations andeither a power source or a ground; and a control circuit for controllingsaid switch circuit to be in an OFF-state in an interval time periodbetween refresh operations for breaking down said leak path and alsocontrolling said switch circuit to turn ON prior to said refreshoperation, so that operations of a power system and a control system arepreviously activated for subsequent start of internal operations forsaid refresh, wherein a consumption of current is reduced with refreshtimings matched between either a read mode or a write mode and astand-by mode.
 2. A semiconductor memory device configured toautomatically refresh data stored in memory cells and to allow anexternal asynchronous access, said device including: a switch circuitinserted into a leak path between a system of circuits associated withrefresh operations and either a power source or a ground; and a controlcircuit for controlling the switch circuit to be in an OFF-state in aninterval of time period between refresh operations for breaking downsaid leak path and also controlling said switch circuit to turn ON priorto said refresh operations, so that operations of a power system and acontrol system are previously activated for subsequent start of internaloperations for said refresh, wherein a consumption of current is reducedwith refresh timings matched between read and write modes and a stand-bymode.
 3. The semiconductor memory device as claimed in claim 2, whereinthe switch circuit includes an MOS transistor having a gate thresholdvoltage which is higher than transistors forming the system of circuitsassociated with the refresh operations.
 4. The semiconductor memorydevice as claimed in claim 1, wherein a power voltage to the system ofcircuits associated with the refresh operations is reduced.
 5. Thesemiconductor memory device as claimed in claim 4, wherein the system ofcircuits associated with the refresh operations includes MOS transistorshaving lower gate threshold voltages adopted to the reduced powervoltage.
 6. The semiconductor memory device as claimed in claim 1,wherein the system of circuits associated with the refresh operationsincludes a transistor, which forms a critical path and has a gatethreshold voltage lower than a transistor forming a non-critical path.7. The semiconductor memory device as claimed in claim 1, wherein thecontrol circuit delays a chip select signal for generating an internalchip select signal so as to break down the leak path based on theinternal chip select signal when the chip select signal for switchingbetween a stand-by mode and an active mode is transitioned from anactivated state into an inactivated state.
 8. The semiconductor memorydevice as claimed in claim 2, wherein a power voltage to the system ofcircuits associated with the refresh operations is reduced.
 9. Thesemiconductor memory device as claimed in claim 8, wherein the system ofcircuits associated with the refresh operations includes MOS transistorshaving lower gate threshold voltages adopted to the reduced powervoltage.
 10. The semiconductor memory device as claimed in claim 2,wherein the system of circuits associated with the refresh operationsincludes a transistor, which forms a critical path and has a gatethreshold voltage lower than a transistor forming a non-critical path.11. The semiconductor memory device as claimed in claim 2, wherein thecontrol circuit delays a chip select signal for generating an internalchip select signal so as to break down the leak path based on theinternal chip select signal when the chip select signal for switchingbetween a stand-by mode and an active mode is transitioned from anactivated state into an inactivated state.
 12. A semiconductor memorydevice, configured to automatically refresh data stored in memory cellsand to allow an external asynchronous access, said device including: aswitch circuit inserted into a leak path between a system of circuitsassociated with refresh operations and either a power source or aground; and a control circuit for controlling the switch circuit to bein an OFF-state in an interval of time period between refresh operationsfor breaking down said leak path and also controlling said switchcircuit to turn ON prior to said refresh operations, so that operationsof a power system and a control system are previously activated forsubsequent start of internal operations for said refresh, wherein aconsumption of current is reduced with refresh timings matched betweenread and write modes and a stand-by mode, wherein the switch circuitincludes an MOS transistor having a gate threshold voltage which ishigher than transistors forming the system of circuits associated withthe refresh operations, wherein a power voltage to the system ofcircuits associated with the refresh operations is reduced, wherein thesystem of circuits associated with the refresh operations includes MOStransistors having lower gate threshold voltages adopted to the reducedpower voltage, wherein the system of circuits associated with therefresh operations includes a transistor, which forms a critical pathand has a gate threshold voltage lower than a transistor forming anon-critical path, and wherein the control circuit delays a chip selectsignal for generating an internal chip select signal so as to break downthe leak path based on the internal chip select signal when the chipselect signal for switching between a stand-by mode and an active modeis transitioned from an activated state into an inactivated state.